Divider and microcomputer including the same

ABSTRACT

A subtraction-shift-type divider using a dividend or partial remainder represented by signed digits taking any of the values -1, 0, 1 and a divisor by twos complement representation. A selector, responding to values of a quotient digit at respective time points during the execution of division, converts the divisor into any of the same value, inverted value or &#34;0&#34; for outputting. An adder adds (subtracts) a partial remainder and 1 or 0. A quotient digit deciding circuit decides the next quotient digit from the quotient digits at respective time points during the execution of division, and a portion of the partial remainder obtained by the adder. The number of transistors constituting an actual circuit can be reduced by using a redundant signal digit (RSD) representation in the same way as the prior art and simplifying tables for deciding the quotient digit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a divider, and particularly, relates toa subtraction-shift-type divider and a microcomputer including suchdivider

2. Description of the Related Art

A principle of subtraction shift-type-division which performs asubtraction between a dividend or partial remainder by RSDrepresentation and a divisor by twos complement representation is shownin pages 748 to 756 of the IEEE, Journal of Solid-State Circuit, Vol.25, No. 3 (June, 1990).

Though various propositions are made as a divider and a processorconforming to the division principle shown in this journal, typical onesare Japanese Patent Application Laid-Open No. 63-49836 (1988), JapanesePatent Application Laid-Open No. 3-102519 (1991) and Japanese PatentApplication Laid-Open No. 2-112023 (1990)

A number by RSD (Redundant Signed Digit) representation is a numericalrepresentation which represents the number of each digit, by {-1, 0, 1},and is expressed as Y in the following expression. ##EQU1##

While, a number by twos complement representation is expressed as Z inthe following expression. ##EQU2##

The above,mentioned number Y by RSD representation and the number Z bytwos complement representation are added as shown in a schematic diagramof FIG. 1, and their sum S is obtained as a number by RSD representationshown in the following expression. ##EQU3##

In FIG. 1, symbols of large ◯ respectively designate full adders, aridsymbols of small ◯ respectively designate inverted inputs to or invertedoutputs from the full adders.

FIG. 2(a) is a schematic diagram showing inputs and outputs to and fromthe full adder shown in FIG. 1, and

FIG. 2(b) is a truth table therebetween.

While, the number Y by RSD representation and the number Z by twoscomplement representation are subtracted as shown in a schematic diagramof FIG. 3, and their difference D is obtained is the number by RSDrepresentation shown in the following expression. ##EQU4##

In FIG. 3, in the same way as FIG. 1, the symbols of large C)respectively designate the full adders and the symbols of small ◯respectively designate the inverted inputs to or the inverted outputsfrom the full adders

Truth tables of the full adders shown in FIG. 3 are similar to thatshown in FIG. 2(b).

Such addition and subtraction of the number Y by RSD representation andthe number Z by twos complement representation can be performed rapidlybecause of free from carry propagations.

In a subtraction-shift-type divider, a quotient digit q_(j) is selectedto satisfy the following expressions (1) and (2) with respect to thepartial remainder (dividend) R_(j) and the divisor D.

    R.sub.j+1 =2·(R.sub.j -q.sub.j ·D)       (1)

    -2·|D|<R.sub.j+1 <2·|D|                         (2)

A selective process of the quotient digit q_(j) satisfying theexpressions (1) and (2) is not one and only but somewhat optional. Forexample, in a restoring division, with respect to the positive partialremainder (dividend) R_(j) and divisor D, the quotient q_(j) is

    q.sub.j ε{0, 1}, and

in an unrestoring division,

    q.sub.j ε{-1, 1}

It is also possible to have

    q.sub.j ε{-1, 0, 1},

and these are used in the principle of division in the aforementionedjournal.

Now, in the principle of division in the aforementioned journal, thequotient digit q_(j) is decided according to a table as shown in FIG.4(a) when the divisor D is positive, and according to a table as shownin FIG. 4(b) when the divisor D is negative. However, hereupon, thedivisor D and the partial remainder R_(j) are as shown in the followingexpression, wherein r₀, r₁, r₂ in FIG. 4(a) and FIG. 4(b) respectivelyshow r_(j), 0, r_(j), 1, r_(j), 2 in the following expression. ##EQU5##

In this way, in the above-mentioned prior art, since there is no carrypropagation in a division cycle, the division can be performed rapidly.Also, since the remainder is given in a binary difference, it is easy toconvert it into a twos complementary representation.

However, since the tables for deciding the quotient digit arecomplicated, at the time of realizing quotient digit deciding means inintegrated circuits and the like as actual circuits, a large number oftransistors are required.

Besides, the divisor value must be standardized.

Furthermore, when the divisor is "-1", the divisor must be extended in alower direction to make a least significant bit apparently "0".

Also, since such divider as aforementioned can not directly give andtake data between a CPU and an ALU of a usual microcomputer, it isnecessary to convert it into the twos complementary representation.

SUMMARY OF THE INVENTION

The present invention has been devised in view of such circumstances,therefore, it is an object thereof to provide a divider, in which, inthe same way as the prior art, an RSD representation is used and tablesfor deciding a quotient digit are simplified to reduce the number oftransistors in case of constituting an actual circuit.

It is another object of the present invention to provide a divider inwhich a divisor is not necessarily standardized, by extracting a portionto be inputted to quotient digit deciding means from a partial remainderaccording to the divisor value to decide the quotient digit.

It is a further object of the present invention to provide a divider, inwhich division can be performed even when the divisor is "-1", just byincreasing a small number of transistors in case of constituting theactual circuit.

It is still another object of the present invention to provide amicrocomputer, in which a dividend and a divisor can be written into thedivider as above-mentioned effectively from a CPU.

It is a still further object of the present invention to provide amicrocomputer, in which a quotient and a remainder can be readeffectively into the CPU from the divider as above-mentioned.

The divider of the present invention is the subtraction-shift-typedivider using the dividend or partial remainder represented by signeddigits taking any of the values -1, 0, 1 and divisor by twos complementrepresentation, and comprises: converting means which, responding tovalues of quotient digit at respective time points during the executionof division, converts the divisor into any of the same value invertedvalue or "0" for outputting; adding means which adds or subtracts thepartial remainder, output of the converting means, and 1 or 0, and nextquotient digit deciding means which decides the next quotient digit fromthe quotient digits at respective time points during the executing ofdivision and a portion of partial remainder obtained by the addition orsubtraction of the adding means responding thereto.

The divider of the present invention is the subtraction-shift-typedivider using the dividend or partial remainder represented by signeddigits taking any of the values -1, 0, 1 and a divisor by twoscomplement representation, and comprises: converting meads whichconverts the divisor responding to quotient digit at respective timepoints during the execution of division; adding means which adds orsubtracts the partial remainder, output of the converting means and 1 or0; next quotient digit deciding means which, responding to the quotientdigits at respective time points during the execution of division,decides the next quotient digit using a portion of the partial remainderobtained by the subtraction of the adding means; and extracting meanswhich, responding to a value of the divisor, extracts a portion from thepartial remainder so as to decide the next quotient digit by the nextquotient digit deciding means.

Furthermore, the divider of the present invention is thesubtraction-shift-type divider using the dividend or partial remainderrepresented by a singed digit taking any of the values -1, 0, 1 and adivisor by twos complement representation, and comprises: convertingmeans which, responding to values of quotient digit at respective timepoints during the execution of division, converts the divisor; addingmeans which adds or subtracts the partial remainder, output of theconverting means and 1 or 0; next quotient digit deciding means which,responding to the quotient digits at respective time points during theexecution of division, decides the next quotient digit using a portionof the partial remainder obtained by the subtraction of the addingmeans; extracting means which, responding to a value of the divisor,extracts a portion from the partial remainder so as to decide the nextquotient digit by the next quotient deciding means; and means forconverting the divisor into "-2" when it is "-1".

A microcomputer of the present invention comprises: a divider, using thedividend or partial remainder represented by signed digits taking any ofthe values -1, 0, 1, and including a first register holding anon-positive portion of the dividend, a second register holding anon-negative portion of the dividend and a third register holding thedivisor; and an ALU respectively connected to the first and secondregisters via a first bus and to the third register via a second bus.

A microcomputer of the present invention comprises: a divider, in whicha quotient or remainder represented by a singed digit taking any of thevalues -1, 0, 1 is used, and including a first register holding anon-positive portion of the quotient, a second register holding anon-positive portion of the remainder, a third register holding anon-negative portion of the quotient and fourth register holding anon-negative portion of the reside; and an ALU respectively connected tothe first and third registers via a first bus and to the second andfourth registers via a second bus.

In the divider of the present invention, responding to the quotientdigits at respective the points during the execution of division, thedivisor is converted into any of the same value inverted value and "0"by the converting means, and the next quotient digit is decided by thenext quotient digit deciding means from the quotient digits atrespective time points during the division, and a portion of the partialreminder obtained by the addition or subtraction of the adding meansresponding thereto.

In the divider of the present invention, responding to the quotientdigits at respective time points during the execution of division, thedivisor is converted by the converting means, and the next quotientdigit is decided by the next quotient digit deciding means, using aportion of the partial remainder obtained by the subtraction of theadding means, responding to the quotient digits at respective timepoints during the execution of division, and further, responding to thedivisor value, a portion of the partial remainder is extracted by theextracting means to decide the next quotient digit by the next quotientdigit deciding means.

Furthermore, in the divider of the present invention, in addition to theabove, the divisor is converted into "-2" for division when it is "-1".

In the microcomputer of the present invention, the division is performedby the divider, by writing a most significant digit of the dividend bytwos complement representation into the first register, and all of theother digits of the dividend into the second register respectivelythrough the first bus, and at the same time, by clearing the portions ofthe first and second registers where data are not written, and bywriting the divisor into the third register through the second bus.

In the microcomputer of the present invention, the content of the firstregister is given to the ALU through the first bus, and the content ofthe third register through the second bus for subtraction to obtain thequotient converted into the twos complement, and the content of thesecond register is given to the ALU through the first bus and thecontent of the fourth register through the second bus for subtraction toobtain the remainder converted into the twos complement.

The above and further objects and features of the invention will morefully be apparent from the following detailed description withaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a configuration for adding anumber by RSD representation and a number by twos complementrepresentation;

FIG. 2(a) is a schematic diagram showing inputs and outputs of fulladders shown in FIG. 1;

FIG. 2(b) is a truth table therebetween;

FIG. 3 is a schematic view showing a configuration for subtracting anumber by RSD representation and a number by twos complementrepresentation;

FIG. 4(a) is a schematic diagram showing a table used for deciding aquotient digit, when a divisor D is positive, by a conventional divisionprinciple;

FIG. 4(b) is a schematic diagram showing a table used for deciding aquotient digit, when divisor D is negative, by a conventional divisionprinciple,

FIG. 5(a) is a schematic diagram showing a quotient digit table used ina divider of the present invention, when a divisor D is positive;

FIG. 5(b) is a schematic diagram showing a quotient digit table used ina divider of the present invention, when a divisor D is negative;

FIG. 6(a) is a schematic diagram showing operations corresponding to thecase where a quotient digit q_(j) is "1";

FIG. 6(b) is a schematic diagram showing operations corresponding to thecase where a quotient digit q_(j) is "-1";

FIG. 6(c) is a schematic diagram showing operations corresponding to thecase where a quotient digit q_(j) is "0";

FIG. 7 is a block diagram showing a configuration of one embodiment ofdivider of the present invention;

FIG. 8 is a circuit diagram showing a detailed configuration of aselector and an adder of a divider of the present invention togetherwith each other;

FIG. 9 is a schematic view showing a truth table of a selector and anadder of a divider of the present invention;

FIG. 10 is a schematic view showing a truth table of a selector and anadder of a divider of the present invention;

FIG. 11 is a circuit diagram showing a configuration of a quotient digitdeciding circuit of a divider of the present invention;

FIG. 12 is a circuit, diagram showing a detailed configuration of a nextquotient digit output circuit of a quotient digit deciding circuit of adivider of the present invention;

FIG. 13 is a timing chart for explaining the operation of a divider ofthe present invention;

FIG. 14 is a circuit diagram showing, together with FIG. 15, a circuitconfiguration of a portion having a function for deciding positions ofX₂, X₁, X₀ from a value of divisor D of a coefficient extracting circuitof a divider of the present invention;

FIG. 15 is a circuit diagram showing, together with FIG. 14, a circuitconfiguration of a portion having a function for deciding positions ofX₂, X₁, X₀ from a value of divider D of a coefficients extractingcircuit of a divider of the present invention;

FIG. 16 is a circuit diagram showing an example of a detailedconfiguration of constituents of a coefficient extracting circuit of adivider of the present invention;

FIG. 17 is a circuit diagram showing an example of a detailedconfiguration of constituents of a coefficient extracting circuit of adivider of the present invention;

FIG. 18 is a circuit diagram showing an example of a detailedconfiguration of constituents of a coefficient extracting circuit of adivider of the present invention;

FIG. 19 is a circuit diagram showing, together with FIG. 20, an exampleof a detailed configuration of constituents of a coefficient extractingcircuit of a divider of the present invention;

FIG. 20 is a circuit diagram showing, together with FIG. 19, an exampleof a detailed configuration of constituents of a coefficient extractingcircuit of a divider of the present invention;

FIG. 21 is a circuit, diagram showing a configuration of a divisorregister of a divider of the present invention;

FIG. 22 is a block diagram showing an example of connection forinstructing a division to a divider of the present invention from amicrocomputer; and

FIG. 23 is a block diagram showing an example of connection foroutputting the results of division by a divider of the present inventionto a microcomputer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, the present invention is particularly described basedon the drawings showing its embodiments.

A divider of the present invention uses a number by RSD representationas a dividend or partial remainder, and a number by twos complementrepresentation as a divisor.

FIG. 5(a) and FIG. 5(b) are schematic diagrams showing quotient digittables respectively used in the divider of the present invention when adivisor D is positive and negative. The divisor of the present inventiondecides the quotient digit according to these tables, which are farsimpler than the quotient digit tables shown in FIG. 4(a) and FIG. 4(b)and used in a conventional divider.

The tables are made for referring serial 3-digit numbers "X₂, X₁, X₀ "at a specific position in a partial remainder R_(j+1) obtained by theresult of operation of the "j"th time and a next quotient digit q_(j+1).

In the quotient digit tables shown in FIG. 5(a) and FIG. 5(b), xindicates not to be referred and q_(j) shows the quotient digit of the"j"th time.

The serial 3-digit numbers at a specific position in the partialremainder R_(j+1) referred to are 3-digit numbers in the partialremainder R_(j+1) whose leading digit corresponds to a last digit ofserial "0" or "1" when viewing the divisor D from a high order.

Schematic diagrams of FIG. 6(a), FIG. 6(b) and FIG. 6(c) show operationscorresponding to three values adoptable by the quotient digit q_(j).

In FIG. 6(a), FIG. 6(b) and FIG. 6(c), in the same way as in theaforementioned conventional FIG. 1 and FIG. 3, a symbol of large ◯indicates a full adder and a symbol of small ◯ indicates inverted inputsto, and inverted outputs from the full adder.

A truth table of the full adders shown in FIGS. 6(a), FIG. 6(b) and FIG.6(c) is same as the conventional truth table shown in FIG. 2(b),

FIG. 6(a) corresponds to the case of "q_(j) =1", and shows a subtractionbetween the partial remainder R_(j) and the divisor D.

FIG. 6(b) corresponds to the case of "q_(j) =-1", and shows an additionbetween the partial remainder R_(j) and the divisor D.

FIG. 6(c) corresponds to the case of "q_(j) =0", and shows an additionbetween the partial remainder R_(j) and the number "0".

FIG. 7 is a block diagram showing a configuration of one embodiment of adivider of the present invention.

The divider of the embodiment shown in FIG. 7 performs mutual divisionof 32 bits

In FIG. 7, numeral 1 designates a first register (hereinafter, referredto as a first register pair), which is constituted in a pair by the tworegisters storing a dividend or a portion of quotient. To the firstregister pair 1, an output of a coefficient extracting circuit 11 to bedescribed later is inputted in synchronism with a second control signalφ₂, and its output is given to a first shifter 3 to be described later.

Numeral 2 designates a quotients digit deciding circuit as quotientdigit deciding means. The output of the coefficient extracting circuit11 to be described later is inputted to the quotient digit decidingcircuit 2, and its output is given to the first shifter 3 and a selector9 to be described later.

The output of the first register pair 1 and the output of the quotientdigit deciding circuit 2 are inputted to the first shifter 3, and itsoutput is given to the shifter 6 and a first latch pair 4 to bedescribed later.

Numeral 4 designates a pair of 32-bit first latch (hereinafter, referredto as a first latch pair), which inputs the output of theabove-mentioned first shifter 3 in synchronism with a first controlsignal φ₁, and holds it temporarily and outputs it to the coefficientextracting circuit 11.

Numeral 8 designates a pair of 32-bit second register (hereinafter,referred to as a second register pair). The output of the coefficientextracting circuit 11 is given in synchronism with the second controlsignal φ₂ to the second register pair 5, and its output is given to thesecond shifter 0.

Numeral 6 designates the second shifter, to which an output of thesecond register pair 8 and the output of the first shifter 3 areinputted as aforementioned, and its output is given to a second latchpair to be described later.

Numeral 7 designates a second latch (hereinafter, referred to as thesecond latch pair), which is a pair of 32-bit latches and inputs theoutput of the second shifter 6 in synchronism with the first controlsignal φ₁, holds it temporarily and outputs it to an input terminal ofan adder 10.

Numeral 8 designates a 32-bit divisor register storing a divisor D. Thedivisor register 8 holds the divisor D given from outside and outputs itto a selector 9 to be described later.

Numeral 9 designates the selector, whose function is shown in FIG. 7 ina symbolized fashion. The selector 9 inputs the divisor D held by thedivisor register 8, and respectively outputs the divisor D intact from aterminal 91, an inverted value of the divisor D from a terminal 92 and"0" from a terminal 93. Responding to the quotient digit given from thequotient digit deciding circuit 2, the selector 9 selects and outputsany of the terminals 91, 92 and 93, specifically, any of the intactdivisor value, the inverted value of the divisor and "0" to a secondinput terminal of the adder 10.

The adder 10 inputs the output of the second latch pair 7, which is thenumber by RSD representation to a first input terminal and inputs theoutput of the selector 9, which is a number by,twos complementrepresentation, to a second input terminal for addition. The result ofaddition by the adder 10 is outputted to the coefficient extractingmeans 11.

Numeral 11 designates the coefficient extracting circuit as thecoefficient extracting means, which extracts the aforementioned serial3-digit numbers at a specific position in the partial remainder R_(j+1),as a coefficient, from the outputs of the adder 10 and the first latchpair 4.

FIG. 8 is a circuit diagram showing a detailed configuration of theselector 9 and the adder 10 together with each other.

In FIG. 8, however, the configuration for one bit is shown, thus theselector 9 and the adder 10 are constituted by arranging thisconfiguration in parallel for 32 bits.

The quotient digit q_(j) is expressed by the following expression.

    q.sub.j =q.sub.j *-q.sub.j **; q.sub.j **, q.sub.j *ε{0, 1}

In FIG. 8, numeral 12 designates an input terminal of the quotient digitq_(j) **, and numeral 13 designates an input terminal of the quotientdigit q_(j) *. Numeral 14 designates a 1-bit input terminal of thedivisor D, numeral 15 designates an exclusive NOR gate and numeral 16designates an exclusive OR gate.

The input terminal 12 is connected to one input of the exclusive NORgate 15, and the input terminal 14 is connected to another inputthereof, and its output is given to one input of a NAND gate 17. Theinput terminal 13 is connected to one input of the exclusive OR gate 16,and the input terminal 14 is connected to another input thereof, and itsoutput is given to another input of the NAND gate 17. An output of theNAND gate 17 is inputted to an inverter 18, whose output is given to anexclusive OR gate 23 and an AND gate 24 to be described later.

By the numerals 15, 16, 17 and 18, an "i"th bit of the selector 9 isconstituted.

Upper 32 bits in the partial remainder or dividend R_(j) are alwaysinputted to the adder 10. The upper 32 bits inputted to the adder 10 aredesignated by R_(j) ,i and expressed by the following expression.

    R.sub.j, i =R.sub.j, i *-R.sub.j, i **; R.sub.j, i **,R.sub.j, i *ε{0, 1}

In FIG. 8,i numerals 19 and 20 designate input terminals, into whichR_(j), i ** and R_(j), i * are inputted respectively from the secondhatch pair 7.

Numeral 21 designates an exclusive OR gate, to one input of which theinput terminal 19 is connected, and to another input thereof, the inputterminal 20 is connected, and its output is given to a NOR gate 23, ANDgate 24 and NOR gate 26 via an inverter 22.

To one inputs of the exclusive OR gate 23, AND gate 24 and NOR gate 26,the output of the inverter 18 is connected, and to the other inputsthereof, the output of the inverter is connected.

Numeral 25 designates an inverter, which inputs the output of theexclusive OR gate 23 and outputs R_(j+1), i **. That is, the output ofthe inverter 25 serves as an output terminal 29 of the R_(j+1), i **.The input terminal 19 is connected to one input of the NOR gate 26, andthe output of the inverter 22 is given to another input thereof asmentioned before. An output of the NOR gate 26 is given to one input ofa NOR gates 27.

To another input of the NOR gate 27, an output of the AND gate 24 isgiven, and its output is given to an inverter 28.

The inverter 28 inputs the output of the NOR gate 27 and outputsR_(j+1), i+1 *. That is, th output of the inverter 28 serves as theoutput terminal 30 of the R_(j+1), i **.

By the numerals 21 to 28, an i bit of the adder 10 is constituted.

The "i"th bit of the adder 10 provides the R_(j+1), i ** and R_(j+1),i+1 * in,

    R.sub.j+1, i =R.sub.j+1, i *-R.sub.j+1, i **, and

    R.sub.j+1, i+1 =R.sub.j+1, i+1 *-R.sub.j+1, i+1 **.

FIG. 9 ant FIG. 10 are schematic views showing truth tables of theselector 9 and the adder 10.

The truth table of FIG. 9 shows output values of a node Z in FIG. 8 foprespective input values of the divisor d_(i) and quotient digits q_(j)*, q_(j) **.

The truth table of FIG. 10 shows output values of the R_(j+1), i **,R_(j+1) * for respective input values of a node Z_(i) and dividendsR_(j), i **, R_(j), i *.

FIG. 11 is a circuit diagram showing a configuration of the quotientdigit deciding circuit 2.

In FIG. 11, numeral 31 designates a next quotient digit output circuit,which inputs serial 3-digit numbers "X₂, X₁, X₀ " at a specific positionin the partial remainder R_(j+1) and a signed bit d₃₁ and the quotientdigit q_(j) of the divisor D, and outputs a next quotient digit q_(j+1).

X₂, X₁, X₀ are expressed as follows,

    X.sub.2 =X.sub.2 *-X.sub.2 **

    X.sub.1 =X.sub.1 *-X.sub.1 **

    X.sub.0 =X.sub.0 *-X.sub.0 **

Numerals 32 to 37 designate input terminals of the next quotient digitoutput circuit 31 for inputting X₂ **, X₂ *, X₁ **, X₁ *, X₀ **, X₀ *.

Numeral 38 designates an input terminal of the next quotient digitoutput circuit 31 of the signed bit d₃₁.

Hereupon, the quotient digit q_(j) is expressed by the followingexpression.

    q.sub.j =q.sub.j *-q.sub.j **

Numerals 39 and 40 designate input terminals of the next quotient digitoutput circuit 31 for inputting q_(j) *, q_(j) ** in the above-mentionedexpression.

The next quotient digit q_(j+1) is expressed by the followingexpression.

    q.sub.j+1 =q.sub.j+1 *-q.sub.j+1 **

Numerals 41 and 42 designate output terminals of the next quotient digitoutput circuit 31 for outputting q_(j+1) **, q_(i+1) *.

The output from the output terminals 41, 42 are given to the firstshifter 3, and respectively to latches 43, 44.

The outputs of the latches 43, 44 are given to the selector 9.

Numeral 45 designates a control terminal for initializing the latches43, 44 to "0".

Numerals 46 and 47 designate latches, respective input terminals ofwhich are connected to the outputs of the latches 43, 44. The outputs ofthe latches 46, 47 serve as the input terminals 39, 40.

Numeral 48 designates an inverter, which inverts the output of the latch43 and gives it to one input of a NAND gate 49.

To another input of the NAND gate 49, the output of the latch 44 isgiven, and its output is given to one input of an exclusive OR gate 50.

Numeral 73 designates an exclusive OR gate, to inputs of which theoutputs of the latches 43, 44 are given. An output of the exclusive ORgate 73 is given to one input of a NAND gate 74.

To another input of the NAND gate 74, a signal DMNS1 is given, and itsoutput is given to another input of the exclusive OR gate 50.

The output of the exclusive OR gate 50 serves as an output terminal 51for outputting R_(j+1), 0 *, which gives the R_(j+1), 0 * in FIG. 6(treated in the same way as the output of the adder 10).

The signal DMNS1 inputted to the NAND gate 74 is a signal which becomes"1" when the divisor value is "-1", and it may be substituted by theinverter when there is no possibility that the divisor value is "-1". Inthat case, the exclusive OR gate 73 as well as the NAND gate 74 are notnecessary.

FIG. 12 is a circuit diagram showing a detailed configuration of theabove-mentioned next quotient digit output circuit 31.

In FIG. 12, numerals 32 to 37 designate input terminals for inputting X₂**, X₂ *, X₁ **, X₁ *, X₀ **, X₀ *.

Numeral 38 designates an input terminal of bit 31 (d₃₁) of the divisorD.

Numerals 39, 40 designate input terminals of q_(j) ** and q_(j) *, andnumerals 41, 42 designate output terminals of q_(j+1) **, and q_(j+1) *.

Numeral 53 designates a NAND gate, one input out which is connected tothe input terminal 34 and another input thereof is connected to theinput terminal 35 via an inverter 52.

Numeral 55 designates a NAND gate, one input of which is connected tothe input terminal 35, and another input thereof is connected to theinput terminal 34 via an inverter 54.

Numeral 56 designates a 3-input NAND gate, a first input of which isconnected to the terminal 36, a second input is connected to the outputof the NAND gate 53, and a third input is connected to the output of theNAND gate 55.

Numeral 57 designates a 3-input NAND gate, a first input of which isconnected to the input terminal 37, a second input is connected to theoutput of the NAND gate 53 and a third input is connected to the NANDgate 55.

Numeral 58 designates a NAND gate, one input of which is connected tothe output of th NAND gate 53, and another input is connected to theoutput of the NAND gate 56.

Numeral 59 designates a NAND gate, one input of which is connected tothe output of the NAND gate 55, and another input is connected to theoutput of the NAND gate 57.

Numeral 60 designates an exclusive OR gate, one input of which isconnected to the input terminal 38, and another input is connected tothe output of the NAND gate 58.

Numeral 61 designates an exclusive OR gate, one input of which isconnected to the input terminal 38, and another input is connected tothe output of the NAND gate 59.

Numeral 62 designates an exclusive OR gate, one input of which isconnected to the input terminal 32, and another input is connected tothe input terminal 33. An output of the exclusive OR gate 62 is given totransfer gates 66 and 65 via an inverter 63, and further, given totransfer gates 68 and 67 via an inverter 64.

Both of the transfer gates 65, 66 are conducted when an output of theinverter 63 is "1", and both of the transfer gates 67, 68 are conductedwhen an output of the inverter 64 is "1".

An input of the transfer gate 65 is connected to the output of theexclusive OR gate 60, and its output serves as the output terminal 41via inverters 69, 70.

An input of the transfer gate 66 is connected to the output of theexclusive OR gate 61, and its output serves as the output terminal 42via inverters 71, 72.

An input of the transfer gate 67 is connected to the input terminal 39,and its output serves as the output terminal 41 via the above-mentionedinverters 69, 70.

An input of the transfer gate 68 is connected to the input terminal 40,and its output serves as the output terminal 42 via the above-mentionedinverters 71, 72.

Next, the operation of the divider of the present invention is describedwith reference to a timing chart of FIG. 13.

In this embodiment, it is assumed that the divisor is not to take avalue "-1".

In FIG. 13, W1 indicates a waveform of the first control signal φ₁, W2indicates a waveform of the second control signal φ₂ and W3 indicates awaveform of a timing for sending a dividend and a divisor to thedivider.

At the time T₀, the dividend is written into the first latch pair 4, andthe divisor is written into the divisor register 8.

At this timing, "0" is written into the second latch pair 7, and thelatches 43, 44 are cleared to "0".

Till the time T₂, "0" is inputted to the adder 10 as q₋₁, q₋₁ *, andsince R₋₁, 0 ** is "0", the output of the adder 10 during this periodbecomes as follows.

    R.sub.0, 31 **=R.sub.0, 31 *= . . . =R.sub.0, 1 **=R.sub.0, 1 *=R.sub.0, 0 **=0

Till the time T₁, the coefficient extracting circuit 11 extracts X₂, X₁,X₀, and sends them to the quotient digit deciding circuit 2. Receivingthem, the next quotient digit output circuit 31 of the quotient digitdeciding circuit 2 decides the quotient digits q₀ ** and q₀ * till thetime T₂, according to the table shown in FIG. 9 or FIG. 10.

At the time T₁, the content of the first latch pair 4 adder 10 is sentto the second latch pair 7.

At the time T₂, lower 31 bits of the content of the first latch pair 4and the quotient digit q₀ decided previously are sent to the first latchpair 4 via the first shifter 3. Simultaneously, lower 31 bits of thecontent of the second register pair 5 and an upper 1 bit of the firstshifter 3 are sent to the second latch pair 7 via the second shifter 6.

At the time T₂, the quotient digits q₀ ** and q₀ * are sent to thelatches 43, 44 and held therein until the time T₄. The selector 9 iscontrolled by the outputs of the latches 43, 44, and further, R₁, 0 * iscomposed.

In the adder 10, the output of the second latch pair 7 and the output ofthe selector 9 are added to output R₁, 31 **, R₁, 31 *, . . . R₁, 1 **,R₁, 1 *, R₁, 0 **.

The coefficient extracting circuit 11 extracts X₂, X₁, X₀ and sends themto the quotient digit deciding circuit 2 till the time T₃.

Receiving them, the next quotient digit output circuit 31 of thequotient digit deciding circuit 2 decides the quotient digits q₁ ** andq₁ * according to the table shown in FIG. 9 or FIG. 10 till the time T₄.

A first cycle of the division is from the time T₂ to time T₄ among theabove-mentioned times. Therefore, the same cycle is repeated 31 times tocomplete the division. In such a manner, at the time point of thecompletion of division, the quotient is stored in the first latch pair 4and the remainder is stored in the second latch pair 7.

FIG. 14 and FIG. 15, FIG. 19 and FIG. 20, FIG. 16, FIG. 17 and FIG. 18are circuit diagrams showing a configuration of the coefficientextracting circuit 11.

FIG. 14 and FIG. 15 respectively show divided diagrams which areoriginally one diagram, and FIG. 19 and FIG. 20 respectively showdivided diagrams which are originally one-diagram, too.

FIG. 14 and FIG. 15 show a circuit configuration of a portion having afunction to decide positions of X₂, X₁, x₀ from the value of the divisorD.

FIG. 16, FIG. 17 and FIG. 18 are the detailed circuit diagrams ofconstituents of the coefficient extracting circuit 11 shown in FIG. 14and FIG. 15.

FIG. 16 shows a configuration of a block designated by reference numeral140 shown in FIG. 14 and FIG. 15.

In FIG. 16, numerals 75 to 78 designate input terminals of bit 31 to bit28 (d₃₁ to d₂₈) of the divisor D.

Numerals 79, 80, 81 respectively designate exclusive OR gates.

One input of the exclusive OR gate 79 is connected to the input terminal75, and another input terminal is connected to the input terminal 76,and its output is given to one input of a NOR gate 82 and an inverter83. One input of the exclusive OR gate 80 is connected to the inputterminal 75, and another input is connected to the input terminal 77,and its output is given to another input of the NOR gate 82 and a NANDgate 84. One input of the exclusive OR gate 81 is connected to the inputterminal 75, and another input is connected to the input terminal 78,and its output is given to a NAND gate 85 and an inverter 86.

An output of the NOR gate 82 is given to one input of the NAND gate 85 ad one input of a NAND gate 87. To another input of the NAND gate 85, theoutput of the exclusive OR gate 81 is given as aforementioned, and itsoutput serves as an output terminal 91 of a signal C₂₈. To another inputof a NAND gate 87, the output of the exclusive OR gate 81 is given viathe inverter 86, and its output serves as an output terminal 92 of asignal Y₇ via an inverter 88.

An output of the inverter 83 is given to one input of the NAND gate 84,and serves as an output terminal 89 of a signal C₃₀. To another input ofthe NAND gate 84, the output of the exclusive OR gate 80 is given asmentioned before, and its output serves as an output terminal 90 of asignal C₂₉.

Thus, in the circuit shown in FIG. 16, bits 31, 30, 29, 28 (d₃₁, d₃₀,d₂₉, d₂₈) of the divisor D are inputted from the input terminals 75, 76,77, 78, and the signals C₃₀, C₂₉, C₂₈ and Y₇ are outputted from theoutput terminals 890, 90, 91 and 92.

FIG. 17 shows a configuration of blocks designated by reference numerals141a to 141f shown in FIG. 14 and FIG. 15.

In FIG. 17, numeral 75 designates an input terminal of the bit 31 (d₃₁)of the divisor D.

Numerals 93 to 96 designate input terminals of bits 4i+3 to4i+0(d_(4i+3), d_(4i+2), d_(4i+1), d_(4i+0)) of the divisor D.

Numerals 97, 98, 99, 100 designate exclusive OR gates, to one inputterminals of which the input terminal 75 is connected.

To another input of the exclusive OR gate 97, input terminal 93 isconnected, and its output is given to one input of a NAND gate 104 andone input of a NAND gate 101. To another input of the exclusive Or gate98, the input terminal 94 is connected, and its output is given to afirst input of 3-input NAND gate 105 and to another input of the OR gate101. To another input of the exclusive OR gate 99, the input terminal 95is connected, and its output is given to a first input of a 3-input NANDgate 106, an input of an inverter 107 and one input of a NOR gate 102.To another input of the exclusive OR gate 100, the input terminal 96 isconnected, and its output is given to a first input of a 4-input NANDgate 108 and to another input of the NOR gate 102.

An output of the NOR gate 101 is given to a second input of the NANDgate 106, a second input of the NAND gate 108 and one input of a NANDgate 109. An output of the NOR gate 102 is given to another input of theNAND gate 109. An output of the NAND gate 109 serves as an outputterminal 115 of a signal Y_(i) via an inverter 110.

Numeral 103 designates an input terminal of a signal Z_(i), and isconnected to another input of the NAND gate 104, a second input of theNAND gate 105, a third input of the NAND gate 106 and a third input ofthe NAND gate 108.

An output of the NAND gate 104 is given to a third input of the NANDgate 105, and serves as an output terminal 111 of a signal C_(4i+3). Anoutput of the NAND gate 105 serves as an output terminal 112 of a signalC_(4i+2). An output of the NAND gate 106 serves as an output terminal113 of a signal C_(4i+1). To fourth input of the NAND gate 108, anoutput of the exclusive OR gate 99 is given via the aforementionedinverter 107, and its output serves as an input terminal 114 of a signalC_(4i+0).

This, in the circuit shown in FIG. 17, the bits 31, 4i+3, 4i+2, 4i+1,4i+0 (d₃₁, 3_(4i+3), d_(4i+2), d_(4i+1), d_(4i+0)) of the divisor D areinputted from the input terminals 75, 93, 94, 95, 96, and the signalsC_(4i+3), C_(4i+2), C_(4i+1), C_(4i+0) and a signal Y_(i) are outputtedfrom the output terminals 11, 112, 113, 114 and 115 respectively.

FIG. 18 shows a configuration of a block designated by reference numeral142 shown in FIG. 14 and FIG. 15.

In FIG. 18, numeral 75 designates an input terminal of a bit 31 (₃₁) ofthe divisor D.

Numerals 116 to 119 respectively designated input terminals of bits 3 to0 (d₃, d₂, d₁, d₀) of the divisor D.

Numerals 120, 121, 122, 123 designate exclusive OR gates, to each of oneinputs of which, the input terminal 75 is connected.

To another input of the exclusive OR gate 120, the input terminal 116 isconnected, and its output is given to one input of a NAND gate 127 andto one input of a NOR gate 124. To another input of the exclusive ORgate 121, the input terminal 117 is connected, and its output is givento a first input of a 3-input NAND gate 128 and another input of the NOrgate 124. To another input of the exclusive OR gate 122, the inputterminal 118 is connected, and its output is given to a first input of a3-input NAND gate 129, an input of an inverter 125 and an input of aninverter 130. To another input of the exclusive OR gate 123, the inputterminal 119 is connected, and its output is given to a first input of a4-input NAND gate 131.

An output of the NOR gate 124 is given to a second input of the NANDgate 129, a second input of the NAND gate 131 and one input of an NANDgate 132, and an output of the inverter 125 is given to anther input ofthe NAND gate 132. An output of the NAND gate 132 serves as an outputterminal 138 of a signal Y₀ via an inverter 133.

Numeral 126 designates an input terminal of a signal Z₀, which isconnected to another input of the NAND gate 127, a second input of theNAND gate 128, a third input of the NAND gate 129 and a third input ofthe NAND gate 131.

An output of the NANd gate 127 is given to a third input of the NANDgate 128, and serves as an output terminal 134 of a signal C₃. An outputof the NAND gate 128 serves as an output terminal 135 of a signal C₂. Anoutput of the NAND gate 129 serves as an output terminal 136 of a signalC₁. To a fourth input of the NAND gate 131, an output of the exclusiveOR gate 122 is given via the aforementioned inverter 130, and its outputserves as an output terminal 137 of a signal C₀.

Thus, in the circuit shown in FIG. 18, the bits 31, 3, 2, 1, 0 (d₃₁, d₃,d₂, d₁, d₀) of the divisor D are inputted from the input terminals 75,116, 117, 118, 119, and the signals C₃, C₂, C₁, C₀ and the signal Y₀ areoutputted from the output terminals 134, 135, 136, 137 and 138.

In FIG. 14 and FIG. 15, numeral 140 designates the circuit shown in FIG.16, and the same numerals designate the same constituents in FIG. 16 andtheir explanation is omitted.

Numerals 141a to 141f designate the circuit shown in FIG. 17, and thesame numerals designate the same constituents in FIG. 17 and theirexplanation is omitted.

Furthermore, numeral 142 designates the circuit shown in FIG. 18, andthe configurations of a block designated by character 143a and a blockdesignated by numeral 143b are same, except that a circuit 141d in theblock 143a is a circuit 142 in the block 143b.

In FIG. 14 and FIG. 15, numeral 144 in a circuit 14a designates a NANDgate, to one input of which a signal Y₇ is inputted, and to anotherinput thereof a signal Y₆ is inputted, and its output serves as a signalZ₅ via an inverter 145.

Numeral 146 designates a 3-input NAND gate, to a first input of which,the signal Y₇ is inputted, to a second input, the signal Y₆ is inputtedand to a third input, a signal Y₅ is inputted. An output of the NANDgate 146 serves as a signal Z₄ via an inverter 47.

Numeral 148 designates a 4-input NAND gate, to a first input of which,the signal Y₇ is inputted, to a second input, the signal Y₅ is inputtedand to a fourth input, a signal Y₄ is inputted. An output of the NANDgate 148 serves as a signal Z₃ via an inverter 149.

Numeral 150 designates a NAND gate, to one input of which, a signal Y₀is inputted and to another input thereof, a signal Z₀ is inputted. Anoutput of the NAND gate 150 serves as an signal NC via an inverter 151.

The signal NC becomes "1" when the bit contents of the divisor D aresimilar to each other except the least significant bit.

When a value of the divisor is not "-1", the NAND gate 150 and theinverter 151 are not necessary.

In FIG. 19 and FIG. 20, numerals 152a to 152g designate input terminalsof outputs R_(j+1), 31 ** to R_(j+1), 0 ** of the adder 10, and numerals153a to 153g designate input terminals of outputs R_(j+1), 31 * toR_(j*1), 0 * of the same.

Numerals 154a to 154f designate input terminals of the signals C₃₀ toC₀.

Numeral 156 designates an inverter, an input of which is connected tothe input terminal 155. Numerals 157a to 157f designate P-channeltransistors, respective sources of which are connected to powerpotentials, and respective gates thereof are connected to an output ofthe inverter 156.

Numerals 159 and 160 designate input terminals inputting an upper 1 bitoutput of the first latch pair 4.

Since numerals 158a to 158r designate circuits having a sameconfiguration, only a circuit configuration 158a is described.

Numeral 161 designates a 3-input NOR gate, a first input of which isconnected to the input terminal 152a, a second input is connected to theinput terminal 154a, and to a third input thereof, the first controlsignal φ₁ is inputted.

Numeral 162 designates a 3-input NOR gate, a first input of which isconnected tot he input terminal 153a, a second input is connected to theinput terminal 154a, and to a third input thereof, the first controlsignal φ₁ is inputted.

An output of the NOR gate 161 is given to a gate of an N-channeltransistor 163. A source of the N-channel transistor 163 is grounded,and a drain is connected to a signal line which is connected to a drainof the P-channel transistor 157a.

An output of the NOR gate 162 is given to a gate of an N-channeltransistor 164. A source of the N-channel transistor 164 is grounded,and a drain is connected to a signal line which is connected to a drainof the P-channel transistor 157b.

A signal line from the input terminal 154a is further wired to theblocks 158g, 158n, and connected to inputs of NOR gates of the blockscorresponding to the NOR gates 161, 162 of the block 158a.

Signal lines from the input terminals 154b to 154e are also same.

A signal line from the input terminal 154f is wired to the blocks 158f,158l and 158m, and similarly, connected to the inputs of the NOr gatesof respective blocks.

Numeral 166a to 166f designate circuits having a same configuration, sothat only the configuration of the block 166a is described. Numeral 167designates a weak latch, which prevents a state of the signal lineconnected to the drain of the P-channel transistor 157a from becoming ahigh impedance.

Numeral 168 designates a latch, which holds a state of the signal lineconnected tot he drain of the P-channel transistor 157a, and inverts itfor output.

Numerals 169 to 174 designate output terminals of X₂ **, X₂ *, X₁ **, X₁*, X₀ **, X₀ *.

Next, the operation is described.

The circuits shown in FIG. 14 and FIG. 15 receive the divisor D anddecide the positions of X₂ to X₀. For example, when the divisor D is"001101 . . . ", a signal C₂₉ becomes "0". The signal C₂₉ is inputted tothe NOR gates of the blocks 158b, 158h, 158o in the circuits shown inFIG. 19 and FIG. 20.

The signal line connected tot he drain of the P-channel transistors 157ato 157f shown in FIGS. 19 and 20 are precharged during the period wherethe first control signal φ₁ is "1". When the first control signal 100 ₁becomes "0", since two inputs of the NOR gates of the blocks 158b, 158h,158o become "0", the state of outputs R_(j+1), 30 ** to R_(j+1), 28 * ofthe adder 10 is transmitted to the signal lines connected to the drainsof the P-channel transistors 157a to 157f.

When the second control signal φ₂ becomes "1", the state of the signallines connected tot he drains of the P-channel transistors 157a to 157fis held by the latch 168 and the like, and inverted for output from theoutput terminals 169 to 174.

The coefficient extracting circuit 11 of this embodiment can also beapplied to the conventional prior-art divider.

Next, the divisor register 8 is described. The divisor register 8 is soconstituted that a division in the case where the divisor D is "-1" canbe performed effectively.

FIG. 21 shows a circuit diagram showing a configuration of the divisorregister 8.

In FIG. 21, numerals 175 to 178 designate memory cells whichrespectively hold the contents from the most significant bit 31 to theleast significant bit 0 of the divisor D.

Numeral 179 designates a 3-input NAND gate, a first input of whichconnected to an output of the memory cell 178, to a second inputthereof, the content d₃₁ of the most significant bit of the divisor D isinputted, and to a third input, the signal NC is inputted.

Numeral 180 designates a NAND gate, to one input of which the output ofthe memory cell 178 is inputted, and another input is connected too anoutput of the NAND gate 179. An output of the NAND gate serves as anoutput terminal 185 via an inverter 181.

Numeral 186 designates an inverter, an input of which is connected tothe output of the NAND gate 179, and its output serves as an outputterminal 200 of a signal DMNS1.

Numerals 182 to 185 designate output terminals which output the divisor,among which, though the output terminals 182 to 184 output the contentsof the memory cells 175 to 177 intact, to the output terminal 185, anoutput of the inverter 181 is outputted.

When the divisor D is "-1", the NAND gate 179 outputs "0". In this case,the output terminals 182 to 185 output "-2", and the signal DNMS1becomes "1".

Receiving the signal DNMS1, the quotient digit deciding circuit 2inverts R_(j+1), 0 * and outputs it when the quotient digit q_(i+1) isnot "0". The R_(j+1), 0 * is inverted by the exclusive OR gate 73, NANDgate 74 and exclusive OR gate 51.

And hence, even when the divisor D is "-1", the division can beperformed in the same way as the case where the divisor D is "-2". Thus,since it is not necessary to extend the divisor D to the lower directionto make the least significant bit of the divisor D apparently "0" torespond to the case where the divisor D is "-1", an excessive transistoris not necessary.

Next, a microcomputer including the divider of the present invention asmentioned above, specifically, the configuration of connection betweenthe ALU, CPU and divider, is described with reference to block diagramsof FIG. 22 and FIG. 23.

At first, in a first embodiment shown in FIG. 22, the connection betweenthe CPU and the divider of the present invention having the basicconfiguration shown in FIG. 7 in the microcomputer, more specifically,the configuration for inputting the dividend and divisor to the dividerof the present invention form the CPU side is shown.

In FIG. 22, numeral 187 designates an X bus in the CPU, numeral 188designates a Y bus in the CPU and numeral 189 designates the ALU of theCPU.

though numerals 4 and 8 designate the first latch pair and the divisorregister of the divider of the present invention shown in FIG. 7, otherportions are omitted.

Numeral 190 designates gate means provided at a position connectingbetween the X bus 187 and a latch 400 holding a non-positive portion ofthe first latch pair 4 of the divider of the present invention, whichwrites the content of the most significant bit of the X bus 187, intothe most significant bit of the latch 400 on the side storing thedividend R₀ ** of the first latch pair 4, and "0" into the other bits.

Numeral 191 designates gate means provided at a position connectingbetween the X bus 187 and a latch 401 holding a non-negative portion ofthe first latch pair 4 of the divider of the present invention, whichwrites the contents of the bits other than the most significant bit ofthe X bus 187, into the bits other than the most significant bits of thelatch 401 on the side storing the dividend R₀ * of the first latch pair4, and "0" into the most significant bit.

Numeral 192 designates gate means provided at a position connectingbetween the Y bus 188 and the divisor register 8 of the divider of thepresent invention, which writes the content of bits of the Y bus 188into bits of the divisor register 8.

In the case where the CPU is constituted to perform operations otherthan the division by the ALU 189, with data on the X bus 187 as anoperand and data on the Y bus 188 as an operand, it is simply possibleto constitute such that, against a division instruction, the content ofdividend is outputted to the X bus 187 and the content of divisor to theY bus 188.

When the aforementioned gate means 190, 191, 192 are operatedsimultaneously in such a case, the divider of the present invention iscapable of taking the dividend into the first latch pair 4 and thedivisor into the divisor register 8 simultaneously, and further,converting the dividend into the RSD representation from the twoscomplement representation.

The configuration of the microcomputer of this embodiment is alsoapplicable in the divider, using the dividend or partial remainderrepresented by signed digits which is any of "-1", "0", "1".

As a next embodiment, a configuration of the microcomputer capable ofreading a quotient and a remainder, which are the result of division,into the CPU effectively from the divider of the present invention isshown.

In FIG. 23, numeral 193 designates gate means, provided at a positionconnecting the Y bus 188 and a register 100 holding a non-positiveportion of the first register pair 1, which outputs the content of theregister 100 on the side storing the dividend (quotient) R₀ * of thefirst register pair 1 to the Y bus 188.

Numeral 194 designates gate means, provided at a position connecting theX bus 187 and a register 101 holding a non-negative portion of the firstregister pair 1, which outputs the content of the register 101 on theside storing the dividend (quotient) R₀ ** of the first register pair 1to the X bus 187.

Numeral 195 designates gate means, provided at a position connecting theY bus 188 and a register 500 holding a non-positive portion of thesecond register pair 5, which outputs the content of the register 500 onthe side storing the partial remainder R_(j) * of the second registerpair 5 to the Y bus 188.

Numeral 196 designates gate means, provided at a position connecting theX bus 187 and a register 501 holding a non-negative portion of thesecond register pair 5, which outputs the content of the register 501 onthe side storing the partial remainder R_(j) ** of the second registerpair 5 to the X bus 187.

In case of reading the quotient obtained by the divider of the presentinvention, at first, the gate means 193, 194 are operatedsimultaneously. Next, when a value outputted on the Y bus 188 issubtracted from a value outputted on the X bus 187 by an ALU 189, aquotient can be obtained as an output of the ALU 189.

On the same way, in case of reading the remainder, at first, the gatemeans 195, 196 are operated simultaneously. Next, when a value outputtedon the Y bus 188 is subtracted from a value outputted on the X bus 187by the ALU 189, a remainder can be obtained as an output of the ALU 189.

Since the ALU 189 includes a function of subtracted the value on the Ybus 188 from the value on the X bus 187, the number of transistors canbe reduced, as compared with the case including a function of convertingthe quotient or remainder into the twos complement representation fromthe RSD representation in the divider.

The configuration of the microcomputer of this embodiment is alsoapplicable to the divider using the dividend or partial remainder,wherein the quotient or remainder is represented by the signed digitwhich is any of "-1", "0", "1".

As particularly described heretofore, according to the divider of thepresent invention, the divider, which uses the RSD representation in thesame way the prior art, and is capable of reducing the number oftransistors in case of constituting an actual circuit by simplifying thetables for deciding the quotient digit, is realized.

Also, the divider, in which the divisor is not necessary to bestandardized, by extracting a portion to be inputted to the quotientdigit deciding means from the partial remainder according to thedivision value to decide the quotient digit, is realized.

Furthermore, the divider, in which the division can be performed evenwhen the divisor is "-1", just by increasing a small number oftransistors in case of constituting the actual circuit, is realized.

Furthermore, according to the microcomputer of the present invention,the microcomputer capable of writing the dividend and divisoreffectively into the divider as aforementioned from the CPU, isrealized.

Still further, the microcomputer capable of reading the quotient andremainder effectively into the CPU from the divider as aforementioned,is realized.

As this invention may be embodied in several forms without departingfrom the spirit of essential characteristics thereof, the presentembodiment is therefore illustrative and not restrictive, since thescope of the invention is defined by the appended claims rather than bythe description preceding them, and all changes that fall within themeets and bounds of the claims, or equivalence of such meets and boundsthereof are therefore intended to be embraced by the claims.

What is claimed is:
 1. A subtraction-shift-type divider using a dividendor partial remainder represented by signed digits taking any of thevalues -1, 0, 1, and a divisor by twos complement representation,comprising:converting means for converting the divisor into any of thesame value, inverter value and "0"; adding means for adding(subtracting) the partial remainder and output of said converting means,and next quotient digit deciding means for providing quotient digits,wherein said next quotient digit deciding means decides the nextquotient digit from the quotient digits at respective time points duringthe execution of division, and a portion of the partial remainderobtained from the addition (subtraction) of said adding means, andconversion of the divisor by the converting means is in response tovalues of the quotient digit at respective time points during theexecution of division.
 2. A subtraction-shift-type divider using adividend or partial remainder represented by signed digits taking any ofthe values -1, 0, 1, and a divisor by twos complement representation,comprising:converting means for converting the divisor into any of thesame value, inverter value and "0"; adding means for adding(subtracting) the partial remainder and output of said converting means,next quotient digit deciding means for providing quotient digits, a nextquotient digit being decided by using a portion of the partial remainderobtained by the subtraction of said adding means responding to quotientdigits at respective time points during the execution of division, andextracting means for extracting a portion from the partial remainder fordeciding the next quotient digit by said quotient digit deciding meansresponding to the divisor value.
 3. A divider as set forth in claim 2,further comprising, means for converting a divisor into "-2" when thedivisor is "-1".